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| ADC150 Programmable Integrating A/D Converter THALER CORPORATION * 2015 N. FORBES BOULEVARD * TUCSON, AZ. 85745 * (520) 882-4000 FEATURES * 24 BIT RESOLUTION * SOFTWARE SELECTABLE FEATURES * 0.5ppm/C MAX. SCALE FACTOR ERROR * 2 ppm MAX. LINEARITY ERROR APPLICATIONS * TEST EQUIPMENT * DATA ACQUISITION * SCIENTIFIC INSTRUMENTS * MEDICAL INSTRUMENTS * AUTO ZERO * SEISMOLOGICAL EQUIPMENT * BUS COMPATIBLE * INTERNAL CLOCK and REFERENCE * LOW POWER CONSUMPTION (0.450 WATTS) * ROBOTIC SYSTEMS * WEIGHING SYSTEMS DESCRIPTION ADC150 is a high performance programmable 24bit integrating A/D converter based on a patented architecture. The integration time and resolution along with the power line cycle selection can be easily programmed through the Mode Control Byte. Type ADC150C ADC150CA ADC150M Temperature Operating Range -25C to +85C -25C to +85C -55C to +125C Max. Scale Factor Deviation 60ppm 30ppm 100ppm ADC150 offers 2 ppm max. linearity error and 1 ppm/C max. scale factor error over the military temperature range. It also has excellent offset stability at 2 ppm max. which the user can auto zero if desired. ADC150's compatibility with popular microcomputer buses increases its ease of application in smart systems. An on-board microprocessor controls all internal functions of the ADC150. Thaler designers have minimized external connections to greatly reduce the problem often encountered when applying ADC's. Operating from 15VDC and a +5VDC power supply, ADC150 is packaged in a hermetically sealed 40-pin ceramic DIP package. Precision test equipment, scientific and medical instruments, and data acquisition systems are primary application areas for the unusually high resolution and accuracy of this ADC. ADC150DS REV. F MAR 00 MAXIMUM RATING SPECIFICATIONS MODEL PARAMETER TEMPERATURE Operating Storage POWER SUPPLY VCC VEE VDD INPUTS Analog Inputs Digital Inputs VEE 0 VCC VDD MIN -55 0 +14 -14 +4 ADC150 MAX 125 160 +16 -16 +6 ADC150 UNITS C C VDC VDC VDC EXTERNAL CONNECTIONS (TOP VIEW) N.C. N.C. N.C. Vee (-15V) Vee (+15V) Vdd (+5V) GND N.C. N.C. N.C. N.C. N.C. D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 N.C. N.C. N.C. N.C. AUTO ZERO RESET N.C. N.C. N.C. MODE CONTROL STATUS 1 STATUS 0 CONVERT OUTPUT ENABLE ANALOG LOW ANALOG HIGH ALTERNATE INPUT N.C. N.C. INTEGRATION CAPACITOR NOTES: 1. Power Supply Decoupling The ADC150 has internal 0.1F decoupling capacitors for all power supply inputs. The internal decoupling capacitors are adequate for applications with relatively short power supply leads (approx. 5") or if additional capacitors are located on a circuit board. For applications with long power supply leads an external capacitor of 10 F on the +/- 15V inputs and 33 F on the +5V input is recommended. 2. Ground The ground connection (pin 7) should be made as solid as possible since ground noise can result in a loss of accuracy. Use of a ground plane is a good approach to maintain the full accuracy of the ADC150. 3. External Components A .68 F polystyrene integration capacitor must be connected to pins 34 and 35 with a lead length not exceeding 2". 4. Analog Inputs In order to avoid differential noise pickup it is recommended to use parallel adjacent lines for the analog inputs (pins 39, 40) on PC boards and shielded lines outside of the PC connections. ADC150 32 31 30 29 28 27 26 25 24 23 22 21 ADC150DS REV. F MAR 00 ELECTRICAL SPECIFICATIONS (Vps = +/- 15V, + 5V, T = 25 Deg. C.) ADC150 ADC150CA ADC150M MAX MIN TYP MAX MODEL PARAMETER ACCURACY Resolution Input Equivalent Noise Offset without Auto Zero Offset with Auto Zero Full Scale Noise (.1-10Hz) @ 10V Nonlinearity Normal Mode Rejection 1 TEMPERATURE STABILITY Offset Full Scale TIME STABILITY Offset Full Scale 2 ERROR ALL SOURCES 24 hrs, +/- 1 Deg. C Amb. 90 days, +/- 5 Deg. C Amb. 1 year, +/- 5 Deg. C Amb. CONVERSION TIME WARM-UP TIME POWER SUPPLY REJECTION +/- 15 VDC 5 VDC 80 80 18 MIN ADC150C TYP MAX MIN TYP 24 1 4 1 100 6 1 2 * 0.2 1.0 * * * 2 0.5 50 * * * * 0.1 0.5 * * * * * * * 60 Bits V ppm ppm ppm Vpp ppm dB * * * * ppm/oC ppm/oC .1 2 * * .0005, 2 .0010, 2 .0015, 2 1067 5 .0003, 2 .0008, 2 .0013, 2 * * ppm/month ppm/24 hrs. * * * * * %, +/- Counts %, +/- Counts %, +/- Counts ms minutes * * * * dB dB ANALOG INPUT CHARACTERISTICS Input Range Bias Current Input Impedance -10.485760 1.2 200 14.5 14.5 4.5 15 15 5 23 24 42 10.485755 3 * * * * * * * * * * * * 0.8 4.0 0.8 4.0 * * * * * * * * * * * * * * * * * * * * * * V nA G V V V mA mA mA POWER SUPPLY VOLTAGES +15 V -15 V 5v POWER SUPPLY CURRENTS +15 V -15 V 5v DIGITAL INPUTS Low High DIGITAL OUTPUTS Low High AUTO ZERO INPUT Low High CONVERT INPUT Low High TEMPERATURE RANGE 0.8 4.0 -25 85 * * * * * -55 125 * V V oC 15.5 15.5 5.5 * * * V V * * * V V 0.8 4.0 * * * * V V * Same as ADC150C Note: 1) 60 Cycle 2) ( Max-Min Value) - Noise(.1-10Hz) ADC150DS REV. F MAR 00 THEORY OF OPERATION In the ADC150 block diagram (see Figure 1), Vhi and Vlow are the inputs. Both are buffered and fed into a differential, voltage controlled, single output current source. This current is added to the reference current at the input of the op amp integrator. The output of the integrator is fed into a Schmitt trigger, which in turn, is fed into the ADC's timing control circuitry. When the integrator output actuates the Schmitt trigger, the timing circuit changes the direction of the reference current source and the integrator begins integrating in the opposite direction. This continues until the Schmitt trigger is actuated again by the integrator and reverses the direction of the reference current. The equation for integration times are: Tp= VXC I ref + I inp Tm= VXC -I ref + I inp The timing control circuitry governs the counters that measure the integration time in both directions. The ADC150's on-board microprocessor is used to calculate the results of the integration equation and perform error corrections. Note that the P automatically performs an auto zero function at startup, but it is recommended to achieve maximum accuracy, that an auto zero be performed again after the ADC150 is fully warmed up. When the P detects a convert signal, it lowers the status lines to indicate that the ADC is involved in a conversion. When it detects a change in slope direction, the P will collect the counts for the integration time. When sufficient counts have been collected, the P performs the calculations described above. When the calculations are complete, the P places the most significant byte in the output buffer and raises the S0 flag. When another pulse is placed on the convert line, the middle byte is placed on the output, the S0 flag is lowered and the S1 flag raised. When the last pulse is placed in the convert line, the least significant byte is placed in the output buffer and both status flags are high indicating that the ADC150 is ready for another conversion. Status line summary: S1 0 0 1 1 S0 0 1 0 1 Conversion in progress. Conversion complete. MSB in output. Middle byte in output register. LSB in output. Ready for next conversion. V = Voltage C= Integration Capacitor Value I ref = Reference Current I inp = Input Current Resolving these equations produces: I inp = I ref Tp - Tm Tp + Tm Tp = Time Positive Tm = Time Negative Vhi Auto Zero Switch Vlow Differential Voltage Controlled Current Source Schmitt Trigger +15V Bidirectional Reference Current Source Current Directional Switch -15V Data Output ii Output Buffer Output Enable Microprocessor i Timing Control and Counter Clock Auto Zero Convert Status Lines ADC150DS REV. F MAR 00 FIGURE 1. BLOCK DIAGRAM CONNECTING THE ADC150 POWER SUPPLIES The power supply lines are connected to pins 4-7. Pin 4 is -15V, pin 5 is +15V, pin 6 is +5V and pin 7 is GND. OUTPUT DATA LINES The output data is available in byte form on pins 13-20. Pin 20 is the Most Significant Bit and pin 13 the Least Significant Bit. The data lines go to a high impedance state when the Output Enable line is at a logic one level. OUTPUT ENABLE (PIN 21) Data is placed on the Output Data Lines by a logic zero on this line. See figure 2 for data output format. CONVERT (Pin22) This line is used to initiate a conversion cycle and to retrieve the output data. The status lines indicate which function will be executed. The first pulse (transition from logic one to logic zero) starts the conversion cycle. Two subsequent pulses are used to place the lower two bytes on the Output Data Lines. See figure 4 for timing diagram. STATUS LINES (Pins 23, 24) These lines indicate the present state of the ADC. When the Convert line receives the first pulse in a conversion cycle the Status Lines go to logic zero, indicating that a conversion cycle is in progress. When the conversion is complete the microprocessor places the MSB of the output data in the output buffer and then raises S0 to a logic one, indicating that the MSB at the output data is available in the output buffer. When the Convert Line is pulsed again the middle byte of the output data is placed in that output buffer and S1 changes to logic one and S0 to logic zero. The third pulse places the LSB of the output data in the buffer and both status lines go to the logic one. The converter is now ready for the next conversion cycle. See figure 5 for timing diagrams. The table below shows a summary of the status code. S1 S0 Conversion in process. 0 0 Conversion complete. MSB in output. 0 1 Middle byte in output register. 1 0 LSB in output. Ready for next conversion. 1 1 MODE CONTROL (Pin 25) This line is used to program the ADC150. The mode control byte (8 bit) is placed on the data bus. Pin 25 is then set to logic high, pin 21 is pulsed low to accept the control byte. Pin 22 is then pulsed low and held low until the status lines return high (~2ms). Pin 21 is then pulsed high and pin 25 is then returned to logic low. The ADC150 has now been reset to the new parameters. See figure 6 for timing diagrams. The mode control byte is defined as follows: Bits 7 and 6 - unused Bits 5 and 4 - 00 Pin 39 signal input, autozero* 01 Pin 38 signal input Bit 3 - 0 60 Hz.* 1 50 Hz. Bits 2,1, 0 - 001 18 Bit 010 20 Bit 011 22 Bit* 100 24 Bit * Factory default settings AUTO-ZERO / RESET (Pin 29) A logic zero on this input will autozero the ADC150 by internally connecting the analog high to analog low. Since the P is reset, the ADC150 reverts to the factory default settings in the EPROM (ie. 22bits, 60Hz, pin 39 analog high). To select a mode different than the default settings, the mode control must be set after auto zero. See figure 3 for timing diagrams. INTEGRATION CAPACITOR (Pin 34, 35) A 0.68 F polystyrene or Mylar must be connected to these pins. Lead length should be as short as possible and not exceed 2". ANALOG INPUTS (Pin 39, 40) Both analog inputs are buffered by op-amps and have a common mode rejection of approximately 80dB minimum. To maintain the full accuracy at the ADC it is recommended to keep the input to analog low to less than 0.1VDC. ADC150DS REV. F MAR 00 OUTPUT DATA REPRESENTATION The output data is represented in BOB (Bipolar Offset Binary) format. The table below shows the output data codes for zero and plus-minus full scale input voltage for the programmable resolution of the converter. Input Voltage 24 Bits 1 LSB = 1.24 V -10.485760 V 0.0 V +10.485755 V High Byte 00 80 FF Output Data Middle Byte 00 00 FF Low Byte 00 00 FF Input Voltage 22 Bits 1 LSB = 5 V -10.485760 V 0.0 V +10.485755 V Output Data High Byte Middle Byte 00 20 3F 00 00 FF Low Byte 00 00 FF Input Voltage 20 Bits 1 LSB = 20 V -10.485760 V 0.0 V +10.485755 V Output Data High Byte Middle Byte 00 08 10 00 00 FF Low Byte 00 00 FF Input Voltage 18 Bits 1 LSB = 80 V -10.485760 V 0.0 V +10.485755 V Output Data High Byte Middle Byte 00 02 04 00 00 FF Low Byte 00 00 FF FIGURE 2 ADC150DS REV. F MAR 00 TIMING DIAGRAMS CONVERT AZ S1 S0 Symbol tAZD tTRST tAZ Parameter AZ Pulse Width Tristate Time AZ Time FIGURE 3. AUTO ZERO CONVERT S1 S0 Symbol tCONZ tSZ tCONV Parameter Convert Pulse Status Delay Convert Time FIGURE 4. CONVERSION (22 Bits) ADC150DS REV. F MAR 00 tSZ tCONZ tTRST tAZD tAZ Min. 0.2 30 400 Typ. Max. Unit s ms ms tCONV Min. 5.0 Typ. Max. 8.0 320 Unit s s ms TIMING DIAGRAMS OE D0 - D7 CONVERT tOEDV MSB MIB LSB tSIR S1 S0 Symbol tOEDV tSIR Parameter OE Delay Status Delay Min. Typ. 45 3.0 FIGURE 5. DATA OUTPUT OE CNVRT S1 tSIR S0 MODE Symbol tSIR tSL tOEDV Parameter Status Delay Status Low OE Delay Min. FIGURE 6. MODE CHANGE ADC150DS REV. F MAR 00 tSL tOEDV Typ. 8.0 45 tSIR Max. Unit ns s Max. 100 Unit s ms ns RESOLUTION 18 BITS 20 BITS 22 BITS 24 BITS LINE CYCLES 1 4 16 64 CONV. / SEC (60/50 Hz) 60 / 50 15 / 12 3.7 / 3.1 1.2 / .93 Line Cycle at 60 Hz = 16.667 ms; 50 Hz = 20 ms FIGURE 7. INTEGRATION TIMES 40-PIN HYBRID PACKAGE INCHES DIM E D A L B2 B Q C P G1 B1 MIN 1.080 2.075 0.155 0.220 .100 typ .018 typ .015 .009 .012 .890 .040 typ .035 .012 .018 .910 MAX 1.100 2.115 0.185 0.240 FIGURE 8. MECHANICAL SPECIFICATIONS NOTES: 1. GOLD PLATING 60 MICRO INCHES MINIMUM THICKNESS OVER 100 MICRO INCHES NOMINAL THICKNESS OF NICKEL ADC150DS REV. F MAR 00 |
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